Publicat: 14 Sep 2009 00:00

Title: Refinement in embedded system design: from system level to hardware/software level
Institution: University of Toulouse, IRIT laboratory

Supervisors :
Iulian Ober ( )
Jean-Michel Bruel ( )
Duration: September 2009 - September 2012
Salary: 1300Euro netto/month
Contact: iulian.ober [at]
Embedded systems are computer systems (hardware/software) which are integrated in a larger system and which in general are designed to control and/or monitor its functioning. Embedded systems are often critical, subject to real-time and other reliability constraints. The application domains are very diverse, ranging from consumer electronics to automotive, to energy grids, to aerospace (the last one is our privileged application domain within the AESE excellence pole). More recently, progress in chip manufacturing has allowed building complex embedded architectures, including specialized processors, memory, buses, device controllers and peripherals on a same chip (such architectures are designated as Systems-on-Chip, or SoC).
The most common development cycle for embedded systems is a V-cycle, in which the design phase proceeds, from a high-level architecture derived directly from requirements, by successive decompositions and refinements, towards hardware/software components code (the descending branch of the V). This is followed by component integration steps, with specific validations performed at each step (the ascending branch of the V).
The main problem faced by practitioners is the absence of an integrated theory allowing them to model the system at different stages of refinement. Today, one can use AADL to capture in detail a system architecture: hardware and software components, connections, flows, etc., but the language is very limited when it comes to expressing the functional aspects of components. On the other hand, the SysML language allows capturing these functional aspects (by block diagrams, state-transition models, interaction models, etc.) but there is no support for linking it with an architecture described in AADL. Finally, when such an architecture is refined towards code (VHDL, SystemC, Ada, SCADE, or any other appropriate implementation language), it is very difficult to automate and to validate the refinement.
Within this thesis, we plan to study this problem of refinement from system level to hardware/software level, using SysML as a pivot language. We will study the methodological aspects of integrating models with different levels of abstraction. We will also look into the combined use of simulation, animation and proof tools developed or used by the different communities (software engineers, hardware engineers, system engineers). Finally, we plan to study the refinement formally from some given angles, such as the temporal correctness.
Context and prerequisites: This PhD thesis is connected to several financed projects in which our team is involved, and the work will be conducted in cooperation with academic and industrial partners. The candidate should have a computer science Masters degree or equivalent, and be competent in model driven engineering and formal methods.

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