This position relates to the development of three-dimensional die-stacked transceiver arrays. 3D die-stacking refers to a wafer-scale process we have developed to place opto-electronic devices directly on top of CMOS ICs. This will provide us with ICs that give us the highest bandwidth density possible.
Within the COSIGN project the PhD student is required to further develop our three dimensional stacking process. In particular we wish to address the following topics:
- Scaling the stacking technology to devices that operate at higher bit-rate
- Scaling the stacking technology to a full wafer-size process
- Develop machine manufacturable packaging technologies for three dimensional devices.
This position refers to the development of printed circuit boards with high density opto-electronic interfaces. The idea behind the PCB boards developed in this PhD project is that they will make use of transceivers developed in PhD Position 1. In particular, the PhD student has to investigate scaling of printed circuit boards to high bandwidth density. We focus on printed circuit boards capable of processing and routing hundreds of parallel channels each operating at 10 Gbps and eventually 25 Gbps.
