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Publicat: 21 Aug 2006 | Vizualizari: 953


SDRAM must be initialized with the proper power-up sequence to the following (JEDEC Standard 21C
1. Apply power and start clock. Attempt to maintain a NOP condition at the inputs
2. Maintain stable power, stable clock, and a NOP condition for a minimum of 200us
3. Issue precharge commands for all banks of the device
4. Issue 8 or more auto-refresh commands
5. Issue a mode register set command to initialize the mode register

The SDRAM has an on-chip mode register which is programmed by the user to select the read latency, burst length, and burst type to be used during read/write operations to the DRAM. After power-up sequence, the MRS command must be issued to initialize the device. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. This command is issued by the low signals of RAS, CAS, CS and WE at the positive edge of the clock and address pins are used to data input. Refer the MRS table for details. Two cycles are required to write the data in mode register. During the the MRS cycle, any command cannot be issued. If vendor want to modify functionality of device, it could be altered by re-programming through the MRS command.



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Firma: Confidential
Nivel cariera: 5 - 10 ani
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Perioada de valabilitate: 2023-01-31 00:00:00 - 2023-02-02 00:00:00